1. Field of the Invention
The present invention relates to a data demodulation apparatus for demodulation of digital data signals such as a pulse code modulation (hereinafter referred to as PCM) playback signal produced from a digital data recording apparatus. In particular, the invention is directed towards a data demodulation apparatus applicable to a playback signal from an optical disc apparatus which has been recorded using NRZ or NRZI modulation.
2. Prior Art Technology
With a prior art optical disc apparatus, the size of each region that is formed on the recording medium to express a "1" state bit of a recording signal is limited by the minimum size of the light spot that is projected onto the disc surface for reading the data during playback operation. For this reason, a method of coding a PCM signal prior to recording has been developed, referred to as the 2, 7 RLLC (run length limited code). With that method, as described for example in Japanese Patent Laid-open No. 55-26494, the minimum distance T.sub.min between transitions of the (2, 7) RLLC signal (e.g. the minimum separation between successive "1" state bits) is greater than the bit separation T.sub.w (i.e. the period between successive bits). This enables the shortest wavelength of the recorded signal to be substantially increased. In general, T.sub.min is based on "1" state bits, i.e. every two successive "1" state bits in the (2, 7) RLLC signal are mutually separated by a plurality of "0" state bits. If such a (2, 7) RLLC signal is then recorded by NRZ modulation, and a playback signal subsequently obtained from the recording medium, the time point of each peak in the playback signal will represent the center of a bit window containing a "1" state bit. Thus by using these time points, e.g. to control a phase locked loop circuit circuit, the clock frequency component of the playback signal can be recovered as a determination timing clock signal. Each time this determination timing clock signal attains a specific phase value (i.e. 0.degree.), a specific bit position (e.g. the center of a bit window of a "1" or "0" bit) in the playback signal is defined, so that the determination timing clock signal can be used to demodulate that signal. Alternatively, if the (2, 7) RLLC signal is recorded by NRZI modulation, the zero-crossing points of the playback signal will indicate the positions of respective "1" bit window centers, and so can be similarly used to recover the clock component of the playback signal.
Such prior art demodulation methods have been generally based on analog techniques for detecting code positions in the playback signal, where the term "code position" as used in the present specification and claims refers to the time-axis position of the center of a bit window defining a "1" state bit in the playback signal. In the case of a (2, 7) RLLC signal, such methods detect the peak points or zero-crossing points of that signal. However there have been proposals for utilizing digital techniques to implement all of the functions of such a data demodulation apparatus. An example of such a prior art proposal, for a data demodulation apparatus to be used with an input signal S.sub.i that has been recorded after applying (8-10) conversion, has been described in an Electronics Communications Conference, Electro-acoustic Research Paper (Japan), 1982, EA82-59. With the (8-10) conversion method, as opposed to the (2, 7) RLLC method, the minimum distance between transitions of the resultant signal is identical to the bit separation of the signal, and hence it is necessary to detect the absolute level of the signal in order to obtain the positions of "1" and "0" code bits. FIG. 1 shows the general configuration of that proposed apparatus. The input signal S.sub.i is first periodically sampled by an A/D (analog-to-digital) converter 508, with a sampling period that is defined by a processing clock signal, and the sample values are then delayed by one period of the processing clock signal by a delay circuit 509. The resultant delayed sample values and the non-delayed sample values are both supplied to each of a phase calculator circuit 511 and a code position detector 510. Output values from the phase calculator circuit 511 and the code position detector 510 are supplied to a digital phase locked loop circuit 517, which produces digital values representing reproduced clock phase .phi..sub.r. A data determiner 518 produced detected data and a determination timing clock. The operation of this apparatus is as follows, referring to the waveform diagram of FIG. 2, defining the bit separation of the input signal S.sub.i as T.sub.w, and the sampling period of the A/D converter 508 (i.e. the processing clock period) as Tw/2. Successive quantized digital data values are obtained, and all of the subsequent processing is executed in synchronism with the processing clock signal, i.e. at the sampling frequency. Due to the operation of delay circuit 509, successive pairs of sample values (e.g. values S1 and S2 in FIG. 2(a)) are supplied in parallel to the phase calculator 511 and position detection circuit 510. Based on these pairs of sample values, the code position detector 510 produces a "1" level output as signal Dec, indicating that a zero-crossing position of the input signal S.sub.i has occurred, when the following condition is detected for two successive sample values S1 and S2: EQU S1.times.S2.ltoreq.0, and S2.noteq.0 (1)
Each time that the above conditions are satisfied, so that a "1" level output is produced from the code position detector 510, the phase calculator 511 computes a value .phi..sub.i which represents the phase difference between that zero crossing point and the timing of sample S2. It can be understood that with this apparatus, each zero-crossing point of the input signal S.sub.i is detected as a reference point of the reproduced clock phase. .phi..sub.i is computed by linear interpolation as: EQU .phi..sub.i ={S2/(S2-S1)}.times.180.degree.+180.degree. (2)
Each value of .phi..sub.i thus obtained is supplied to the phase locked loop circuit 517, and substracted from the output value .phi..sub.r produced from the loop, to obtain a phase error .phi..sub.e. If .phi..sub.i is valid, i.e. actually corresponds to a detected code position, it is transferred through a switch 513 and attenuator 517, to be applied to compensate the value of .phi..sub.r.
Judgement as to whether a "1" or a "0" bit position of the input signal S.sub.i has been detected is executed for each sampling time point as follows. A determination timing clock signal is derived by the data determiner 518 from the reproduced clock phase .phi..sub.r, as illustrated in FIG. 2(e). During each interval (beginning with a sample S2) in which that determination timing clock signal is at the "1" level, if the two consecutive sample values S1 and S2 are both positive, then a "1" level output (i.e. a "1" bit) is produced as the detected data, while if the sample values S1 and S2 are both negative, then a "0" level output (a "0" bit) is produced as the detected data. If the two consecutive sample values are of mutually different sign, then this indicates that a zero-crossing point of the input signal has occurred, so that no determination of a "1" or "0" bit state can be made. Computations to obtain such detected data bits, designated in the following as Data, are executed as follows:
If S1.times.S2&lt;0, EQU Data=sgn((S1-S2).times..phi..sub.r +S2.times.180.degree.)
If S1.times.S2.gtoreq.0, EQU Data=sgn(S1) (3)
Where sgn (.) signifies "the sign of (.)", i.e. with Data representing a "1" logic level if a positive sign is obtained, and a "0" level if a negative sign is obtained.
The above apparatus has three disadvantages. Firstly, it is not applicable to an input signal S.sub.i which has been generated by (2, 7) RLLC modulation, and can only demodulate an (8-10) converted signal. Secondly, it is necessary to execute multiplication operations to perform data determination. The need to perform multiplications, results in substantial circuit scale and complexity. Thirdly, with that and all similar types of data demodulation apparatus which utilize A/D conversion of the input signal S.sub.i, the sampling period of the conversion can be no greater than one half of the bit separation T.sub.w of the input signal S.sub.i. Thus, a high sampling frequency must be used, while in addition all processing of the sample values and subsequent computation operations etc. must be performed using a processing clock frequency that is identical to the sampling frequency. This is difficult to implement if the bit rate of the input signal S.sub.i is very high.
It would be advantageous if such a data demodulation apparatus could function with a sampling frequency that is substantially lower than the input signal S.sub.i bit rate. However this has not been possible in the prior art, due to a fundamental problem which arises from the fact that the sampling signal source and the input signal source are different. Even if the sampling frequency is set very precisely to the nominal value of bit rate of a playback signal applied as an input signal, in a practical recording/playback apparatus there will be various degrees of random or periodic variations in the bit rate of the input signal. Even if that bit rate is absolutely constant, with no phase drift, any slight difference between the sampling frequency and the input signal S.sub.i bit rate will result in periodic drift of the phase relationship between the sampling signal and the input signal S.sub.i out of one (0.degree. to 360.degree.) range to another range. This is illustrated in FIGS. 3(a) and 3(b), in which a reproduced clock phase (representing the phase of a clock component of the input signal) is derived based on detecting each peak point of the input signal as a code position. The input signal portion shown represents a bit sequence of "0" "0" "1" "0" "0" "0", with a bit separation of T.sub.w. Each point at which the reproduced clock phase reaches 0.degree. is a determination time point, which defines a bit position of the input signal S.sub.i. If the sampling frequency is slightly higher than the bit rate of the input signal S.sub.i, then a condition shown in FIG. 3(a) will periodically occur, in which two samples S.sub.n-1 and S.sub.n occur within a single bit period of the input signal S.sub.i. Thus, no determination time point is established for the sample period between S.sub.n-1 and S.sub.n. Conversely, if the sampling frequency is slightly lower than the bit rate of the input signal S.sub.i, then a condition shown in FIG. 3(b) will periodically occur, in which two samples S.sub.n-2 and S.sub.n-1 respectively occur just before and just after a single bit period of the input signal S.sub.i, i.e. there are two determination time points within the sampling period S.sub.n-2 to S.sub.n-1. Such a condition will occur for example once in every 100 sampling periods, if the frequency of the clock signal component of the input signal S.sub. i (i.e. bit rate) is 1% higher than the sampling frequency of the A/D converter 1.
The conditions shown in FIGS. 3(a), 3(b) can also occur randomly, due to the effects of jitter in the playback signal. Operation of a prior art data demodulation apparatus such as that described above is based on the fact that a single determination time point always occurs within every second sampling period, and it has not been practicable in the prior art to utilize a sampling period that is substantially identical to the bit separation, for A/D conversion of a playback PCM signal prior to demodulation by a data demodulation apparatus.